/*****************************************************************************
 *
 * Copyright (c) 2018-19, Eduard Gerlits, Paula Herber, Josef Treus
 * Westfälische Wilhelms-Universität Münster, AG Embedded Systems 
 * All rights reserved.
 *
 * This file is part of SysCSec
 *
 * SysCSec is free software: you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation, either version 3 of the License, or (at your
 * option) any later version.
 *
 * SysCSec is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with SysCSec.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 *  Please report any problems or bugs to: sysc.sec@uni-muenster.de
 *
 ****************************************************************************/
#include <systemc.h>
#include "modInv.h"
#include "inputModInv.h"

#define __TIMEOUT__ 1000

int sc_main(int sc_argc, char* sc_argv[]){
	
	// 1.Elaboration

	// instantiate clock 
	sc_clock clk("clk",10, SC_MS);

	// Modules
	InputModule input("input");
	ModInvModule modInv("modInv");

	// connect clock
	input.clk(clk);
	modInv.clk(clk);

	/// HARDWARE PORTS (inputMap -> MAP)

	// y
	sc_signal<sc_biguint<160> > y_sig;
	input.y(y_sig);
	modInv.y(y_sig);

	// m
	sc_signal<sc_biguint<160> > m_sig;
	input.m(m_sig);
	modInv.m(m_sig);

	// en
	sc_signal<bool> en_sig;
	input.en(en_sig);
	modInv.en(en_sig);

	// out
	sc_signal<sc_biguint<160> > out_sig;
	input.out(out_sig);
	modInv.out(out_sig);

	// done
	sc_signal<bool> done_sig;
	input.done(done_sig);
	modInv.done(done_sig);


	// 2. Execution

	sc_start(__TIMEOUT__, SC_MS);
	
	return 0;
}
