/*****************************************************************************
 *
 * Copyright (c) 2018-19, Eduard Gerlits, Paula Herber, Josef Treus
 * Westfälische Wilhelms-Universität Münster, AG Embedded Systems 
 * All rights reserved.
 *
 * This file is part of SysCSec
 *
 * SysCSec is free software: you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation, either version 3 of the License, or (at your
 * option) any later version.
 *
 * SysCSec is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with SysCSec.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 *  Please report any problems or bugs to: sysc.sec@uni-muenster.de
 *
 ****************************************************************************/


#ifndef _MAP_H_
#define _MAP_H_

#include <systemc.h>
#include "commons.h"
#include "modAdd.h"
#include "modSub.h"
#include "modMul.h"
#include "modDiv.h"

/*
This is a SystemC model of a modular arithmetic processor. It encapsulates the hardware modules for single operations and is controled via opcode port.
*/

SC_MODULE(MAPModule){

	/// in

	// Clock
	sc_in<bool> clk;

	// First Operand
	sc_in<sc_biguint<160> > x;

	// Second Operand
	sc_in<sc_biguint<160> > y;

	// Modulo value
	sc_in<sc_biguint<160> > m;

	// Opcode
	sc_in<sc_uint<3> > opcode;

	/// channels

	// Internal input channels for en ports of the hardware modules
	sc_signal<bool> mod_add_en_sig;
	sc_signal<bool> mod_sub_en_sig;
	sc_signal<bool> mod_mul_en_sig;
	sc_signal<bool> mod_div_en_sig;

	// Internal output channels

	// out
	sc_signal<sc_biguint<160> > mod_add_out_sig;
	sc_signal<sc_biguint<160> > mod_sub_out_sig;
	sc_signal<sc_biguint<160> > mod_mul_out_sig;
	sc_signal<sc_biguint<160> > mod_div_out_sig;

	// done
	sc_signal<bool> mod_add_done_sig;
	sc_signal<bool> mod_sub_done_sig;
	sc_signal<bool> mod_mul_done_sig;
	sc_signal<bool> mod_div_done_sig;

	/// out

	// computed value
	sc_out<sc_biguint<160> > out;

	// signals when computation is finished
	sc_out<bool> done;

	// Hardware modules for modulo operations
	ModAddModule mod_add;
	ModSubModule mod_sub;
	ModMulModule mod_mul;
	ModDivModule mod_div;


	// Processes
	void mux_out();
	void mux_done();
	void enable_decoder();

	int mode;
	SC_HAS_PROCESS(MAPModule);
	MAPModule(sc_module_name name, int mode): sc_module(name), mod_add("mod_add", mode), mod_sub("mod_sub", mode), mod_mul("mod_mul", mode), mod_div("mod_div", mode){
		
		this->mode = mode;

		// Connecting
		mod_add.clk(clk);
		mod_sub.clk(clk);
		mod_mul.clk(clk);
		mod_div.clk(clk);

		//	x(x_sig);
		mod_add.x(x);
		mod_sub.x(x);
		mod_mul.x(x);
		mod_div.x(x);

		//y(y_sig);
		mod_add.y(y);
		mod_sub.y(y);
		mod_mul.y(y);
		mod_div.y(y);

		//m(m_sig);
		mod_add.m(m);
		mod_sub.m(m);
		mod_mul.m(m);
		mod_div.m(m);

		//opcode(opcode_sig);
		mod_add.en(mod_add_en_sig);
		mod_sub.en(mod_sub_en_sig);
		mod_mul.en(mod_mul_en_sig);
		mod_div.en(mod_div_en_sig);

		//out(out_sig);
		mod_add.out(mod_add_out_sig);
		mod_sub.out(mod_sub_out_sig);
		mod_mul.out(mod_mul_out_sig);
		mod_div.out(mod_div_out_sig);

		//	done(done_sig);
		mod_add.done(mod_add_done_sig);
		mod_sub.done(mod_sub_done_sig);
		mod_mul.done(mod_mul_done_sig);
		mod_div.done(mod_div_done_sig);
		
		// Processes
		SC_METHOD(mux_out);
		sensitive << clk;

		SC_METHOD(mux_done);
		sensitive << clk;

		SC_THREAD(enable_decoder);
		sensitive << clk;

	}

};

#endif
