/*****************************************************************************
 *
 * Copyright (c) 2018-19, Eduard Gerlits, Paula Herber, Josef Treus
 * Westfälische Wilhelms-Universität Münster, AG Embedded Systems 
 * All rights reserved.
 *
 * This file is part of SysCSec
 *
 * SysCSec is free software: you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation, either version 3 of the License, or (at your
 * option) any later version.
 *
 * SysCSec is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with SysCSec.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 *  Please report any problems or bugs to: sysc.sec@uni-muenster.de
 *
 ****************************************************************************/
#include <systemc.h>
#include "MAP.h"
#include "FW.h"
#include "inputFW.h"

#define __TIMEOUT__ 150000

int sc_main(int sc_argc, char* sc_argv[]){
	
	// 1.Elaboration

	// instantiate clock 
	sc_clock clk("clk",10, SC_MS);

	// Modules
	InputFWModule input("input");
	FWModule fw("fw");
	MAPModule map("map");

	// connect clock
	fw.clk(clk);
	map.clk(clk);

	/// HARDWARE PORTS (FW -> MAP)

	// x
	sc_signal<sc_biguint<160> > x_sig;
	fw.map_x(x_sig);
	map.x(x_sig);

	// y
	sc_signal<sc_biguint<160> > y_sig;
	fw.map_y(y_sig);
	map.y(y_sig);

	// m
	sc_signal<sc_biguint<160> > m_sig;
	fw.map_m(m_sig);
	map.m(m_sig);

	// opcode
	sc_signal<sc_uint<3> > opcode_sig;
	fw.map_opcode(opcode_sig);
	map.opcode(opcode_sig);

	// out
	sc_signal<sc_biguint<160> > out_sig;
	fw.map_out(out_sig);
	map.out(out_sig);

	// done
	sc_signal<bool> done_sig;
	fw.map_done(done_sig);
	map.done(done_sig);


	/// SOFTWARE PORTS (inputFW -> FW)

	// ecc_control
	sc_fifo<sc_uint<4> > ecc_control_sig;
	fw.ecc_control(ecc_control_sig);
	input.ecc_control(ecc_control_sig);

	// data0
	sc_fifo<sc_biguint<160> > data_in0_sig;
	fw.data_in0(data_in0_sig);
	input.data_in0(data_in0_sig);

	// data1
	sc_fifo<sc_biguint<160> > data_in1_sig;
	fw.data_in1(data_in1_sig);
	input.data_in1(data_in1_sig);

	sc_fifo<sc_biguint<160> > data_in2_sig;
	fw.data_in2(data_in2_sig);
	input.data_in2(data_in2_sig);

	sc_fifo<sc_biguint<160> > data_in3_sig;
	fw.data_in3(data_in3_sig);
	input.data_in3(data_in3_sig);

	sc_fifo<sc_biguint<160> > data_in4_sig;
	fw.data_in4(data_in4_sig);
	input.data_in4(data_in4_sig);

	sc_fifo<sc_biguint<160> > data_in5_sig;
	fw.data_in5(data_in5_sig);
	input.data_in5(data_in5_sig);

	sc_fifo<sc_biguint<160> > data_in6_sig;
	fw.data_in6(data_in6_sig);
	input.data_in6(data_in6_sig);

	sc_fifo<sc_biguint<160> > data_in7_sig;
	fw.data_in7(data_in7_sig);
	input.data_in7(data_in7_sig);

	sc_fifo<sc_biguint<160> > data_in8_sig;
	fw.data_in8(data_in8_sig);
	input.data_in8(data_in8_sig);

	sc_fifo<sc_biguint<160> > data_in9_sig;
	fw.data_in9(data_in9_sig);
	input.data_in9(data_in9_sig);


	/// SOFTWARE PORTS (FW -> inputFW)

	// ecc_control
	sc_fifo<sc_uint<2> > ecc_status_sig;
	fw.ecc_status(ecc_status_sig);
	input.ecc_status(ecc_status_sig);

	// data0
	sc_fifo<sc_biguint<160> > data_out0_sig;
	fw.data_out0(data_out0_sig);
	input.data_out0(data_out0_sig);

	// data1
	sc_fifo<sc_biguint<160> > data_out1_sig;
	fw.data_out1(data_out1_sig);
	input.data_out1(data_out1_sig);

	sc_fifo<sc_biguint<160> > data_out2_sig;
	fw.data_out2(data_out2_sig);
	input.data_out2(data_out2_sig);

	sc_fifo<sc_biguint<160> > data_out3_sig;
	fw.data_out3(data_out3_sig);
	input.data_out3(data_out3_sig);

	sc_fifo<sc_biguint<160> > data_out4_sig;
	fw.data_out4(data_out4_sig);
	input.data_out4(data_out4_sig);

	sc_fifo<sc_biguint<160> > data_out5_sig;
	fw.data_out5(data_out5_sig);
	input.data_out5(data_out5_sig);


	// 2.Execution

	sc_start(__TIMEOUT__, SC_MS);
	
	return 0;
}
