/*****************************************************************************
 *
 * Copyright (c) 2018-19, Eduard Gerlits, Paula Herber, Josef Treus
 * Westfälische Wilhelms-Universität Münster, AG Embedded Systems 
 * All rights reserved.
 *
 * This file is part of SysCSec
 *
 * SysCSec is free software: you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation, either version 3 of the License, or (at your
 * option) any later version.
 *
 * SysCSec is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with SysCSec.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 *  Please report any problems or bugs to: sysc.sec@uni-muenster.de
 *
 ****************************************************************************/


#include "modAdd.h"
#include <iostream>
#include "RessourceHandler.cpp"


void ModAddModule::exe(){

	while(true){

		while(en->read()==false){

			wait();
		}
		// 1.Clock Cycle: Initialize internal Registers 
		// Internal Registers

		sc_biguint<160> U1 = 0;
		sc_biguint<160> U2 = 0;

		sc_biguint<160> V = x->read();
		sc_biguint<160> A = y->read();
		sc_biguint<160> P = m->read();
		wait();

		// 2.Clock Cycle: Compute "x + y"
		U1 = V + A;
		wait();

		// 3.Clock Cycle: If x+y>m, subtract m 
		if(U1>=P){
			U2 = U1 - P;
		}
		else {
			U2 = U1;
		}
		
		wait();

		// 4th Clock Cycle
		// Write output values
		out->write(U2);
		done->write(true);

		wait();

		// 5th Clock Cycle
		// enable signal must be reset after distribution of the result
		// before the module goes back to initial state
		while(en->read()==true){
			wait();
		}
		done->write(false);
		wait();
	}

}
